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// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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// Agreement, Intel FPGA IP License Agreement, or other applicable 
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// agreement for further details.
		
module rst_gen
(
input     rst_n,          //Async reset

input     clk,

output    rst_sync_n

);

reg       rst_d_n;
reg       rst_dd_n;

assign    rst_sync_n        =   rst_dd_n;


always @(posedge clk or negedge rst_n) begin
   if(~rst_n) begin
	   rst_d_n              <=   1'b0;
		rst_dd_n             <=   1'b0;
	end
	else begin
	   rst_d_n              <=   1'b1;
		rst_dd_n             <=   rst_d_n;
	end
end

endmodule
